1. Field of the Invention
The present invention relates to an AFC (Automatic Frequency Control) circuit. In particular, the present invention relates to an AFC circuit used for a transceiver of FSK (Frequency Shift Keying) modulation that starts up the power only at the time of data transmitting and receiving, and requires intermittent operation of frequency synchronization.
2. Description of Related Art
In the field of wireless communications that perform intermittent operation (operates only at the time of data transmitting and receiving), reduction of power consumption of the transceiver is proceeding. In order to achieve low power consumption, it is required to reduce the power consumption at the time of the transceiver operation. Generally, an AFC circuit adjusts a frequency error using a pilot signal which is added to data in the wireless communications. However, such AFC circuit adds the pilot signal to the data, and thus the processing time of transmission and reception of data in the transceiver increases. The AFC circuit is necessary in order to improve reliability of the wireless communications. The AFC circuit is expected to reduce power consumption at the time of operation and be capable of adjusting the frequency error by a short pilot signal.
Therefore, a technique capable of adjusting a frequency error by a short pilot signal is disclosed in U.S. Pat. No. 7,352,831. FIG. 4 is a block diagram of an AFC circuit disclosed in U.S. Pat. No. 7,352,831.
An AFC circuit 300 includes a quadrature receiver 310, a demodulator 320, a digital frequency measurement system 330, and a loop 340. The quadrature receiver 310 performs frequency conversion using multipliers 311 and 312 to an IF (Intermediate Frequency) frequency which represents a difference between a frequency of an FSK modulated input signal Vin 201 and a PLL (Phase Locked Loop) 343, so as to generate FSK modulated analog quadrature input signals I202 and Q203.
The digital frequency measurement system 330 generates a digital output signal 204, which represents a center frequency of the analog quadrature input signal 1202 and the analog quadrature input signal Q203.
The loop 340 uses a combining circuit 341 and an adjustment circuit 342 to calculate a frequency error signal Ferr 206 which represents a frequency error between the IF frequency converted as mentioned above and a target IF frequency 205. The loop 340 feeds back the frequency error signal Ferr 206 to the PLL 343, and adjusts an oscillation frequency of the PLL 343. Further, the loop 340 adjusts a difference between the frequency of input signal Vin 201 and the oscillation frequency of the PLL 343 to be the target IF frequency 205, which is output to the demodulator 320, and outputs an output signal 207 with no frequency error.
Hereinafter, the digital frequency measurement system 330 is explained with reference to FIGS. 5 and 6.
The center frequency of the analog quadrature input signals I202 and Q203 is usually an IF frequency. The IF frequency is a frequency greater than or equal to 0 Hz. As for the frequency of the analog quadrature input signals I202 and Q203, the IF frequency plus the frequency deviation (Fdev) indicates a data value “1” (the part indicated by the numeral 209) of binary data 208, and the IF frequency minus the frequency deviation (Fdev) indicates a data value “0” (the part indicated by the numeral 210) of the binary data 208.
The digital frequency measurement system 330 extracts the center frequency (IF frequency) of the analog quadrature input signals I202 and Q203 indicating the binary data 208.
An input signal to a differentiator 331 is a digital signal 1211 with a value of ±1. An output signal by the differentiator 331 is a differentiated signal 212 with a value of ±2. An input signal to a differentiator 332 is digital signal Q213 with a value of ±1. An output signal by the differentiator 332 is a differentiated signal 214 with a value of ±2.
A signal processing circuit (multiplier) 333 multiplies the digital signal 1211 by the differentiated signal 214, and outputs a multiplied signal 215. A signal processing circuit (multiplier) 334 multiplies the digital signal Q213 by the differentiated signal 212, and outputs a multiplied signal 216.
A subtractor 335 subtracts the multiplied signal 216 from the multiplied signal 215, and outputs a density signal 217. The density signal 217 has a pulse density which is proportional to the frequency of the analog quadrature input signals I202 and Q203. For example, the pulse density of the period indicated by the curly bracket B is greater than that of the period indicated by the curly bracket A. This is because that the data value of the binary data 208 is “1” in the period indicated by the curly bracket B. The digital filter 336 of FIG. 5 outputs an output signal Volpf 218. The output Volpf 218 represents an average value of the pulse density of the density signal 217. If the data value of the binary data 208 changes from “0” to “1”, the frequency increases, and the average value of the pulse density of the output signal Volpf 218 also increases.
An envelope detector 337 calculates a midpoint of a maximum value Voh and a minimum value Vol of the output signal Volpf 218, and outputs a digital signal Voed (digital output signal) 204. The digital output signal 204 represents the center frequency of the analog quadrature input signals I202 and Q203 which are equivalent to the binary data 208. The digital output signal 204 can be calculated by two symbols “0” and “1” of the data values of the binary data 208.
Next, the loop 340 is explained with reference to FIG. 4.
The combining circuit 341 calculates a difference between the digital output signal 204, which is the center frequency of the analog quadrature input signals I202 and Q203, and the target IF frequency 205, and outputs a multiplied error signal 220.
The adjustment circuit 342 multiplies the multiplied error signal 220 by a scaling coefficient 221, and outputs the frequency error signal Ferr 206.
The AFC control system 344 filters the frequency error signal Ferr 206 and outputs an error signal 222 so as to provide stability to the loop 340.
An adder 345 adds the error signal 222 and fine frequency adjustment signal 223, and outputs a composite input signal 224.
The PLL 343 oscillates at a frequency, which is shifted by the composite input signal 224 including the frequency error from the frequency determined by a reference input signal 225 generated by the crystal oscillator 346 and an input N 226, and outputs an adjusted local oscillated signal 227.
A quadrature generator 347 generates a cosine quadrature signal 228 and a sine quadrature signal 229 from the adjusted local oscillator signal 227, and outputs the generated signals to the quadrature receiver 310.
Incidentally, Japanese Unexamined Patent Application Publication No. 8-139771 discloses an FSK receiver that uses an output signal demodulated by a demodulator to increase a gain to a gain variable amplifier. Further, Japanese Unexamined Patent Application Publication No. 9-83594 discloses an AFC circuit capable of operating independently from BTR (Bit Timing Recovery) by obtaining a frequency deviation Δω using a detection signal of an oversampling cycle, which is supplied by a reception filter. However, techniques disclosed in Japanese Unexamined Patent Application Publication Nos. 8-139771 and 9-83594 are not purposed to reduce power at the time of AFC circuit operation.